Integrated circuit technology has revolutionized various fields including computers, control systems, telecommunications, and imaging. There are a number of types of semiconductor imagers, including charge coupled devices, photodiode arrays, charge injection devices, and hybrid focal plane arrays. Some sensors are referred to as active pixel image sensors (APS). An active pixel image sensor is defined as an image sensor technology that has one or more active transistors within the pixel unit cell. Some types of active pixel sensor technologies include the amplified MOS imager (AMI), charge modulation device (CMD), volt charge modulated device (VCMD), base stored image sensor (BASIS), and the static induction transistor (SIT).
It is desirable in image sensors to remove fixed pattern noise (FPN) from the signals that are processed from the pixels. One prior art circuit for reducing fixed pattern noise is shown in “Progress in CMOS Active Pixel Sensors,” by S. K. Mendis et al., Proceedings of the SPIE—The International Society for Optical Engineering, Volume 2172, 1994, pages 19-29. The circuit shown in the Mendis et al. reference is patented in U.S. Pat. No. 5,471,515 to Fossum et al. FIG. 3 of the Fossum et al. patent is reproduced herein as FIG. 1.
FIG. 1 is a simplified schematic diagram of one pixel cell of a focal plane array of many such cells formed in an integrated circuit. Referring to FIG. 1, a photogate consists of a relatively large photogate electrode 30 overlying a substrate 20. A charge transfer section consists of a transfer gate electrode 35 adjacent to the photogate electrode 30, a floating diffusion 40, a reset electrode 45, and a drain diffusion 50. A readout circuit consists of a source follower field effect transistor (FET) 55, a row select FET 60, a load FET 65, and correlated double sampling circuit 70.
The readout circuit 70 consists of a signal sample and hold (S/H) circuit including an S/H FET 200 and a signal store capacitor 205 connected through the S/H FET 200 and through the row select FET 60 to the source of the source follower FET 55. The other side of the capacitor 205 is connected to a source bias voltage VSS. The one side of the capacitor 205 is also connected to the gate of an output FET 210. The drain of the output FET is connected through a column select FET 220 to a signal sample output node VOUTS and through a load FET 215 to the drain voltage VDD. A signal called “signal sample and hold” (SHS) briefly turns on the S/H FET 200 after the charge accumulated beneath the photogate electrode 30 has been transferred to the floating diffusion 40, so that the capacitor 205 stores the source voltage of the source follower FET 55 indicating the amount of charge previously accumulated beneath the photogate electrode 30.
The readout circuit 70 also consists of a reset sample and hold (S/H) circuit including an S/H FET 225 and a signal store capacitor 230 connected through the S/H FET 225 and through the row select FET 60 to the source of the source follower FET 55. The other side of the capacitor 230 is connected to the source bias voltage VSS. The one side of the capacitor 230 is also connected to the gate of an output FET 240. The drain of the output FET 240 is connected through a column select FET 245 to a reset sample output node VOUTR and through a load FET 235 to the drain voltage VDD. A signal called “reset sample and hold” (SHR) briefly turns on the S/H FET 225 immediately after the reset signal RST has caused the resetting of the potential of the floating diffusion 40, so that the capacitor 230 stores the voltage to which the floating diffusion has been reset.
The readout circuit provides correlated double sampling of the potential of the floating diffusion, in that the charge integrated beneath the photogate 12 each integration period is obtained at the end of each integration period from the difference between the voltages at the output nodes VOUTS and VOUTR of the readout circuit 70. This eliminates the effects of kTC noise because the difference between VOUTS and VOUTR is independent of any variation in the reset voltage RST, a significant advantage.
The feature of the circuit of FIG. 1 which is useful for eliminating fixed pattern noise due to variations in FET threshold voltage across the substrate 20 is a shorting FET 116 across the sampling capacitors 205 and 230. After the accumulated charge has been measured as the potential difference between the two output nodes VOUTS and VOUTR, a shorting signal VM is temporarily applied to the gate of the shorting FET 116 and the VOUTS-to-VOUTR difference is measured again. This latter difference is a measure of the disparity between the threshold voltages of the output FETs 210, 240, and may be referred to as the fixed pattern difference. The fixed pattern difference is subtracted from the difference between VOUTS and VOUTR measured at the end of the integration period, to remove fixed pattern noise.
As discussed above, the fixed pattern noise that is produced in CMOS image sensors is related to the fact that there are different column amplifiers for each column of a CMOS image sensor pixel array. Column amplifiers generate column fixed pattern noise due to circuit and process variations. As described above, the circuit of FIG. 1 compensates for the fixed pattern noise by subtracting a second differential signal from the first sensed differential signal. As shown in FIG. 1, the difference between the signals of the capacitors for both the first and second differential signals is obtained from an analog subtraction circuit that includes the differential amplifier that amplifies the difference between the signals VOUTS and VOUTR.
One problem with the fixed pattern noise compensation method of FIG. 1 is that in low light environments, if the pixel signal is low, then the gain of the signal amplifier must be increased. If the gain of the signal amplifier is increased, then the fixed pattern noise canceling rate of the above circuit will decrease because of the analog subtraction circuit's inherent errors that result from process variations.
The present invention is directed to a method and apparatus that overcome the foregoing and other disadvantages. More specifically, the present invention is directed to a method and apparatus for reducing fixed pattern noise through the use of a digital subtraction method.